1. Field of Invention
The present invention relates an integrated circuit. More particularly, the present invention relates to a data buffer system.
2. Description of Related Art
Data buffer systems are widely used in various electronic circuits, such as a memory device. For example, a data buffer system of the memory device is configured for transferring data signals in accordance with a read command or a write command. However, voltage variation and noise may significantly affect the performance of the data buffer system, which may fail the operation of the memory device in certain cases.
FIG. 1A is a circuit diagram of a data buffer system 100 according to a prior art. FIG. 1B is a wave diagram of the data buffer system 100. As shown in FIG. 1A, the data buffer system 100 includes a plurality of data buffers 120. The data buffer 120 includes a plurality of inverters 122 electrically coupled in cascade. Each of inverters 122 is driven directly by a supply voltage VCC. The voltage variation may exist in the supply voltage VCC, as shown in FIG. 1B, when the supply voltage goes high (i.e., high VCC), the time difference between the data signal VDATAIN01 and the data signal VDATAOUT01 is short, and the power consumption of the data buffer system 100 is increased. Alternatively, when the supply voltage goes low (i.e., low VCC), the time difference between the data signal VDATAIN01 and the data signal VDATAOUT01 is long, and the power consumption of the data buffer system 100 is decreased. If the time difference between the data signal VDATAOUT01 of the High VCC and the data signal VDATAOUT01 of low VCC is too large, the read/write operation of the memory device may be failed.
FIG. 1C is a circuit diagram of a data buffer system 100a according to another prior art. FIG. 1D and Fig. 1E show wave diagrams of the data buffer system 100a. The data buffer system 100a includes an amplifier 140, a PMOS 160 and a plurality of data buffers 120. The data buffer 120 includes a plurality of inverters 124 electrically coupled in cascade as well. The amplifier 140 and the PMOS 160 are configured for generating a regulated voltage VINT to drive all of the inverters 124. The data buffer system 100a can reduce the voltage variation on the supply voltage VCC, but the regulated voltage VINT suffers from noise generated by data switching in the inverters 124. For example, as shown in Fig.1D, the data signal VDATAIN01 is switched through one of the data buffers 120, and the other data signals VDATAIN02 and DATAIN03 are not switched. In this case (i.e., 1 data signal switching case), the data signal VDATAOUTO1 can be generated normally. And, as shown in FIG. 1E, the data signal VDATAIN01, VDATAIN02 and VDATAIN03 are switched through the corresponding buffer 120. In this case (i.e., all data signals switching case), because the regulated voltage VINT is varied by the switching noise from the buffers 120, the time of the data signal VDATAOUTO1 may vary.
Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.